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8 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF080
Not Recommended for New Designs
Table 1: Pin Description
Symbol Pin Name
SCK Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
SO
CE#
WP#
RST#/
Serial Data Input
Serial Data Out-
put
Chip Enable
Write Protect
Reset
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See
“End-of-Write Detection” on page 15 for more information.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To reset the operation of the device and the internal logic. The device powers on with
HOLD#
Hold
RST# pin functionality as default.
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence; see “Reset/Hold Mode” on page 7.
V DD
V SS
Power Supply
Ground
To provide power supply voltage: 1.65-1.95V for SST25WF080
T1.0 25024
?2012 Silicon Storage Technology, Inc.
5
DS25024B
03/12
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